The invention relates to a CMI decoder for the translation of CMI coded signals into binary signals with differential amplifiers connected to the input side.
From German patent document DE-OS No. 3033351 is known a coder to generate signals in CMI code. This code involves a two-stage NRZ code in which a zero character is represented by the combination of a half-bit long logic "1" signal followed by a half-bit long logic "0" signal whereas continuous 1 characters appear as alternating logic "1" and logic "0" characters of full bit length. This CMI code is defined by the CCITT for the 140 Mbit/s interfaces in the hierarchic structure of a digital signal transmission in Recommendation G.703.
A CMI decoder is known from the Hewlett Packard Service Manual for the measuring instrument "Error Detector" HP 3763 A FIG. A4-3, Part 2. The known CMI decoder has two differential amplifiers disposed at the input side of the decoder. The output of one differential amplifier being connected directly to a gate network and the output of the other being connected via delay sections to the gate network. Due to the use of five OR/NOR circuits the design of the known CMI decoder is costly, and when used in remotely fed arrangements the high power input may also play a role.
For the correct regeneration of the signals it is necessary to obtain a clock signal from the CMI signal received. As is known, this is not easily achieved because, as may be seen from lines E and B of FIG. 3, in CMI signals pulse lengths may range between 0.5 times ans 1.5 times a bit length. Therefore, obtaining a signal of a clock frequency in proper phase by simply filtering it out of CMI coded signals is impossible. For this reason the state of the art requires a subsequent decoder, an expensive circuit with five more gates and other components to obtain a clock signal.